1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a dynamic random access memory (DRAM) formed on an SOI (Silicon On Insulator) substrate.
2. Description of the Background Art
A semiconductor memory device is typically divided into a volatile memory such as a RAM, and a non-volatile memory such as a ROM. The volatile memory is further divided into a DRAM and a static random access memory (SRAM). The non-volatile memory includes a mask ROM, an EPROM, a flash memory, an EEPROM, a fuse ROM, and the like.
A DRAM has data stored by accumulating charge in the capacitor of a memory cell. Although such a DRAM requires a refresh operation, a DRAM having a large storage capacity can be manufactured at a low cost due to its simple structure of the memory cell.
Because data is stored by accumulating charge in a capacitor in a DRAM, the amount of charge stored in a capacitor is altered according to a particles emitted from its package or interconnection material. This change in the amount of charge will result in data inversion, i.e., soft error.
The demand for DRAMs having a higher integration density is also great. The potential of mass production is appreciable for DRAMs having a large storage capacity such as 256M bits and 1G bits. Although the gate length is generally reduced to increase the integration density of a DRAM, this reduction in gate length has a limitation due to a significant short channel effect as the channel length is reduced.
In recent years, large scaled integrated circuits (LSI) are developed having circuit elements such as transistors formed on an SOI substrate with an insulation layer buried in the semiconductor substrate.
FIG. 92 is a plan view showing a structure of a MOS transistor formed on an SOI substrate. FIGS. 93 and 94 are sectional views of the MOS transistor shown in FIG. 92 taken along lines 93--93 and 94--94, respectively.
Referring to FIGS. 92-94, an MOS transistor includes an n.sup.+, type source region 1, an n.sup.+ type drain region 2, a p type body region 3, and a gate electrode 4. Body region 3 is located between source region 1 and drain region 2. When a predetermined potential is applied to gate electrode 4, a channel is formed in body region 3.
This MOS transistor is completely enclosed by a LOCOS oxide film 5 for isolation from an adjacent element. This MOS transistor is formed on an SOI substrate 6. SOI substrate 6 includes a silicon substrate 7, a buried oxide film 8 of SiO.sub.2, and an SOI active layer 9. Source region 1, drain region 2, and body region 3 are formed in this SOI active layer 9.
Body region 3 attains a floating state electrically since it is enclosed by LOCOS oxide film 5 and isolated from silicon substrate 7 by buried oxide layer 8. When body region 3 attains a floating state, the breakdown voltage between the source and drain becomes as low as approximately 3V due to a parasitic bipolar operation. There is also a possibility of a leakage current flow between the source and the drain. Furthermore, a body region 3 attaining a floating state induces the generation of a kink to disturb the drain current Id-drain voltage Vd characteristics. Therefore, the transistor cannot operate stably.